The field of the present invention pertains to the field of integrated circuit design optimization using electronic design automation tools. More particularly, aspects of the present invention pertain to a circuit design optimization process for use in the design of complex integrated circuits with computer aided design (CAD) tools.
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society""s reliance on such systems is likewise increasing, making it critical that the systems deliver the expected performance and obey the properties that their designers intended. As each successive generation of computer and software implemented systems and processes become more powerful, the task of designing and fabricating them becomes increasingly difficult.
The design and manufacture of increasingly complex integrated circuits involves extensive use of CAD tools. The development of ASICs (application specific integrated circuits) and other complex integrated circuits using CAD tools is referred to as electronic design automation, or EDA. The design, checking, and testing of large-scale integrated circuits are so complex that the extensive use of CAD and EDA tools are required for realization of modern, complex integrated circuits.
The development of a new integrated circuit device begins with a design phase involving extensive use of CAD tools to facilitate various aspects of designing the new integrated circuit device. Typically, CAD tools function in part by decomposing the overall desired behavior of the integrated circuit into simpler functions which are more easily manipulated and processed by the CAD tool. The CAD tool performs considerable computation to generate an efficient layout of a resulting xe2x80x9cnetworkxe2x80x9d of design elements (e.g., logic gates, storage elements, etc.). The resulting network, commonly referred to as a netlist, comprises a detailed specification defining the integrated circuit, typically in terms of a particular fabrication technology (e.g., CMOS). The netlist can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Netlists for integrated circuit designs can represent a particular integrated circuit in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Design engineers typically define netlists using one of two popular forms of HDL, Verilog, and VHDL. Via the HDL defined netlist, the integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels, and gate levels). For example, an RTL level netlist is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions (e.g., netlists) can represent all of these levels.
The HDL description is used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a xe2x80x9csilicon compilerxe2x80x9d or xe2x80x9cdesign compilerxe2x80x9d). The compiler program processes the HDL description of the integrated circuit and generates therefrom a low-level netlist comprised of detailed lists of logic components and the interconnections between these components. The components specified by the netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections.
Prior art FIG. 1 shows an exemplary flow chart diagram of a typical prior art logic synthesis process 100. Process 100 is implemented in a CAD environment within a computer system. Process 100 begins in step 101, where an HDL description of the integrated circuit is received (e.g., from a design application). In step 102, the HDL description is compiled by a specialized HDL compiler tool. The compiler (also called an HDL compiler, RTL synthesizer, or architectural optimizer) inputs the HDL description and compiles this description using logic optimization procedures and mapping procedures which interface with a technology-dependent cell library 103 (e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library 103 contains specific information regarding the cells of the specific technology selected. Such information includes, for example, the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library 103. The compiling procedure of step 102 ultimately generates a gate level mapped netlist that is technology dependent, having cells specifically selected in accordance with the particular manufacturing technology being used to fabricate the integrated circuit device.
In step 104, the compiler then performs optimization processing on the resulting mapped netlist from step 102. The optimization processing is performed using a set of design constraints 105. The gate level netlist received from step 102 is processed in light of the design constraints 105. Design constraints 105 include the set of performance constraints applicable to the design, which typically include timing, area, power consumption, and other performance-related limitations that the compiler (e.g., in step 102) will attempt to satisfy when synthesizing the integrated circuit design. These constraints can also include non-performance related constraints such as structural and routing constraints.
Referring still to step 104 of prior art FIG. 1, constraints are used to guide the optimization and mapping of a design towards feasible realization in terms of area, performance, costs, testability, power consumption, and other physical limitations. The constraints provide the goals for the optimization and synthesis tools to achieve. Performance and area constraints are. the two most common constraints. For example, for behavioral synthesis, the area constraints are usually specified at the architectural level where a designer specifies the number of function units, registers, and busses to be used on the RTL structure. The timing constraints are specified as the expected clock frequency of each clock signal.
Technology libraries 103 and design constraints 105 typically contain all the information needed by the synthesis tool to make correct choices in building the structure of the integrated circuit. They contain descriptions of the behavior of a cell and information such as the area of the cell, the timing of the cell, the capacitance loading of the cell, the rise and fall delay values for the basic cells, etc. The objective of the optimization process is to generate the most efficient detailed layout of the integrated circuit possible.
Subsequently, in step 106, the resulting optimized netlist is simulated to verify its performance. In step 107, if the optimized netlist performs as desired, the resulting verified netlist proceeds to subsequent fabrication processing and is fabricated into a resulting integrated circuit device. However, should performance of the optimized netlist prove sub-standard, additional optimization processing and simulation is performed until the netlist can be verified.
The increasing size and complexity of modern integrated circuit devices lead to numerous problems with prior art process 100. The compiling and optimization of large integrated circuit designs are very resource and computer intensive. The compiling and optimization a large integrated circuit designs typically require one, or more, of the most powerful CAD workstations. Large amounts of memory required to store the details regarding the various aspects of the netlist and large amounts of CPU time are required to perform the various compilation and optimization routines on the netlist.
Thus, large complex integrated circuit designs do not lend themselves to efficient optimization using prior art processes, such as process 100. Optimization processing on large design as shown by the steps 104-107 is often cost and time prohibitive. This leads to a number of serious consequences. For example, successive passes through steps 104-107, as is often required in order to optimize a design completely, can be very impractical. Because of this, large designs are typically not optimized is vigorously as smaller designs. This leads to fabricated integrated circuit devices which are less than optimally efficient (e.g., larger than necessary die size, slower performance, greater power consumption, and the like).
For this reason, it is typical for large integrated circuit designs to be broken down into separate circuit blocks which each block independently being subjected to one or more of the steps of process 100. Specifically, xe2x80x9ccharacterizationxe2x80x9d refers to the process of setting up distinct circuit blocks of a large circuit design to be optimized independently, outside of the whole integrated circuit design. For instance, assume a circuit design, E, contains circuit blocks: A; B; C; and D. Circuit E has specified timing constraints and timing exceptions. Characterization automatically generates timing constraints and exceptions which are appropriate for the optimization of blocks A, B, C and D, independently. When optimizing the blocks, the optimization tool 104 (FIG. 1) need only load and process one block at a time. This decreases the demand of the tool on the computer resources. After the blocks have been optimized, they are then re-assembled back into circuit E. One example of the characterization described above is the xe2x80x9ccharacterizexe2x80x9d command found in the above referenced Design Compiler tool from Synopsys.
Accordingly, what is required is a system capable of efficiently optimizing large complex integrated circuit designs. What is acquired is a system capable of vigorously optimizing a complex integrated circuit design within the reasonable time and resource constraints of modern EDA design synthesis processes. What is further required is a system capable of optimizing all portions and all aspects of a complex integrated circuit design. The present invention provides a novel solution to these requirements.
The present invention provides a system capable of efficiently optimizing large complex integrated circuit designs. The present invention provides a method and system for vigorously optimizing a complex integrated circuit design within the reasonable time and resource constraints of modern EDA design synthesis processes. Additionally, the present invention provides a method and system capable of optimizing all portions and all aspects of a complex integrated circuit design.
In one embodiment, the present invention is implemented as an optimization process within a computer-implemented synthesis system. The optimization process functions with other design synthesis tools within the synthesis system (e.g., a CAD workstation) to optimize a gate level netlist of an integrated circuit device in light of specific design constraints. Using modeling technology in accordance with the present invention, optimization occurs in an incremental manner, at a top level of the netlist and at the one or more included circuit block levels of the netlist, such that the entire netlist is optimized while efficiently utilizing the memory and processing resources of the CAD workstation.
The optimization process includes the computer-implemented steps of accessing a circuit netlist representing an integrated circuit design to be realized in physical form (e.g., from a design application), wherein the circuit netlist includes a top-level block and at least a first and a second circuit block. The top-level block includes glue logic and other types of connection circuitry and couples/interfaces the first and second circuit blocks. The optimization process creates a first model of the first circuit block and a second model of the second circuit block. The models are created using modeling technology in accordance with the present invention, wherein the models include sufficient information to describe timing aspects and timing exceptions that are applicable to the first and second circuit blocks respectively.
With this information, the first and second models function by abstracting the embodying circuitry of the first block and the second block, including design constraint dependencies, such as timing constraints and timing exceptions. The first and second models require much less memory and computer resources to store and simulate than the first and second circuit blocks themselves. Hence, the first and second circuit blocks within the top-level block are replaced by their respective models, thereby greatly reducing the amount of memory and computer resources required to store and simulate the top-level block. This allows the entirety of the integrated circuit device to be optimized in a piece-wise fashion wherein multiple blocks can be optimized simultaneously, e.g., in parallel.
In block and top optimization, the entire circuit netlist is optimized by independently optimizing the first circuit block and the second circuit block using characterization. The first and second circuit blocks within the top-level block are replaced by their respective models, thereby allowing the top-level block to be independently optimized within the finite resources of the CAD workstation. Then, the optimized top-level block and the optimized first and second circuit blocks are recombined, yielding a fully optimized circuit netlist. In so doing, all portions and all aspects of the complex integrated circuit design are efficiently optimized, at both the top level and the one or more included circuit blocks.
In a bottle optimization embodiment of the present invention, the circuit blocks are optimized simultaneously with a selected part of the top-level circuit block. Each circuit block has a unique selected part of the top-level circuit which does not overlap the selection of any other part. This selected part of the top-level circuit is the glue logic and connections which are connected closest to the outputs of a particular circuit block. The particular circuit block is optimized with the selected part of the top level circuit.
In an in-context embodiment of the present invention, the circuit blocks are individually optimized within the context of the top level circuit. In-context optimization runs at the top-level of the chip. It is enabled by the use of models in place of all but one or just a few circuit blocks. Optimization is then run at the top-level. This allows the optimization of the remaining circuit blocks (those not replaced by models) with the top level circuit.